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2026-06-15 09:57:51 +08:00
parent a9341db9c8
commit be39714c5e
16 changed files with 423 additions and 181 deletions
@@ -67,6 +67,76 @@ class SysPara;
 #define WARN_STATUS_HDINT			(1<<1)		/*喷头盖，盖上为0，否则为1,必须盖上才能打印,电磁铁有正反面*/
 #define WARN_STATUS_VISCOTITY_MEASURE_READY	(1<<0) // 球已经到上位等灯

+#define PRINT_CTRL_ADDR_BASE	0xa400
+
+#define PRINT_DIGITAL_CHAR_BASE_ADDR	(0xe000)
+
+#define WRITE_CALENDAR_DAT_ADDR		(0xb100)
+
+#define RECYCLE_SLOT_STOP		0x1
+#define RECYCLE_SLOT_CLOSE		0x2
+#define RECYCLE_SLOT_OPEN		0x0
+#define PRINT_START_STOP_CTRL		(PRINT_CTRL_ADDR_BASE + 0x40)
+#define PRINT_RESET_PRODUCT_CNT		(PRINT_CTRL_ADDR_BASE + 0x41)
+#define RECYCLE_SLOT_CTRL_ADDR		(PRINT_CTRL_ADDR_BASE + 0x42)
+#define RESUME_FAULT_ADDR		(PRINT_CTRL_ADDR_BASE + 0x43)
+
+#define VAR_CNT_ADDR			(PRINT_CTRL_ADDR_BASE + 0x50)
+#define VAR_CTRL_REG_ADDR		(PRINT_CTRL_ADDR_BASE + 0x51)
+#define MAININKCTRL_ADDR                (PRINT_CTRL_ADDR_BASE + 0x59)
+//#define MAININKCTRL_ADDR            (PRINT_CTRL_ADDR_BASE + 0x5a)
+#define	WRITE_CNT1GROUP_COUNT               0xB13E
+#define	WRITE_CNT1GROUP_NUM                 0xB13F
+#define	WRITE_CNT1GROUP_SETTING             0xB140
+#define READ_CNT1GROUP_CURR_LOOP  			0x0190
+#define READ_CNT1GROUP_CURR_INDEX			0x0194
+
+#define FPGA_STATUS_BASE_ADDR	0x0000
+#define	 FPGA_VERSOIN_NUM		(FPGA_STATUS_BASE_ADDR + 0xfe)
+
+
+#define	 READ_BUILD_DAT		(FPGA_STATUS_BASE_ADDR + 0xf0)
+
+#define	READ_PRINTDATA_XOR		(FPGA_STATUS_BASE_ADDR + 0xf2)
+#define	READ_SYNC_COUNTER		(FPGA_STATUS_BASE_ADDR + 0xf4)
+
+#define PHASE_DETECT_HIGH_VOLTAGE_TM		0x100
+#define READ_CALENDAR_DAT_ADDR			0x180
+
+#define READ_RAND_FIFO_ADDR			0x200 // 读FPGA的随机码FIFO
+
+#define ROW_PRINT_SEQNENCE_ADDR		0xb200			//行扫描顺序
+#define DAC_TABLE_ADDR			0xb280			//每一个行点对应的DAC值
+#define NOT_GAP_DAC_TABLE_ADDR			0xb380			//每一个不隔点对应的DAC值
+#define FULL_COL_DAC_TABLE_ADDR			0xb480			//每一个不隔点对应的DAC值
+
+#define MATCH_FULL_DAC_TABLE_ADDR       0xB500          // 匹配满列 DAC表 起始地址
+#define MATCH_1_DAC_TABLE_ADDR          0xB600          // 匹配单点 DAC表 起始地址
+#define MATCH_2_DAC_TABLE_ADDR          0xB700          // 匹配两点 DAC表 起始地址
+#define MATCH_3_DAC_TABLE_ADDR          0xB800          // 匹配三点 DAC表 起始地址
+#define MATCH_4_DAC_TABLE_ADDR          0xB900          // 匹配四点 DAC表 起始地址
+#define MATCH_5_DAC_TABLE_ADDR          0xBA00          // 匹配五点 DAC表 起始地址
+#define MATCH_G1_DAC_TABLE_ADDR         0xBC00          // 匹配空一点 DAC表 起始地址
+#define MATCH_G2_DAC_TABLE_ADDR         0xBC80          // 匹配空两点 DAC表 起始地址
+#define MATCH_G3_DAC_TABLE_ADDR         0xBD00          // 匹配空三点 DAC表 起始地址
+#define MATCH_G4_DAC_TABLE_ADDR         0xBD80          // 匹配空四点 DAC表 起始地址
+#define MATCH_G5_DAC_TABLE_ADDR         0xBE00          // 匹配空五点 DAC表 起始地址
+#define MATCH_G6_DAC_TABLE_ADDR         0xBE80          // 匹配空六点 DAC表 起始地址
+#define MATCH_P1_DAC_TABLE_ADDR         0xBF00          // 匹配预备一 DAC表 起始地址
+#define MATCH_P2_DAC_TABLE_ADDR         0xBF80          // 匹配预备二 DAC表 起始地址
+#define MATCH_C_DAC_TABLE_ADDR          0xC000          // 匹配复杂 DAC表 起始地址
+
+#define WRITE_COUNTER3_ADDR		(0xb150)
+#define WRITE_COUNTER4_ADDR		(0xb164)
+//#define READ_CNT3_CURVALUE_ADDR			0x01b4
+#define READ_CNT3_CURVALUE_ADDR			0x1834
+
+#define LOCADDR '1'
+
+#define NOLEDLIGHT 0x10
+#define REDLIGHTCODE 0X11
+#define YELLOWLIGHTCODE 0X13
+#define GREENLIGHTCODE 0X12

 #define FPGA_SYS_HZ		100000000